RIO Developer Essentials Guide for Academia

The RIO Developer Essentials Guide for Academia teaches students the NI RIO platform, which consists of a host PC, two processing targets, the real-time (RT) processor and FPGA. This guide focuses on LabVIEW features for the RT and FPGA and how to interface the targets from a host PC through different communication protocols. The instructions demonstrate various concepts through the use of example LabVIEW codes and step-by-step videos. The download contains an HTML file, which can be viewed online or offline. The index.html to takes you to the main page, where you can navigate to other sections. The LabVIEW examples are stored in the zip folder.
by Dr. Ed Doering | Rose-Hulman Institute of Technology

LEARNING OBJECTIVES


  • Students will learn the fundamentals of a RIO system and learn to identify the PC host, FPGA, and real-time (RT) target in a LabVIEW project.
  • Students will be able to utilize common LabVIEW Real-Time features to manage time, import VHDL and IP block, pass data between host PC, FPGA, and RT targets through various communication protocols.
  • Given a project, students will be able to design an application that can run in parallel and be able to deploy the application to the target as a startup program.
 

COURSE ALIGNMENT

 
Level University
Topic Programming, Embedded System Architectures, Networking, FPGA
Style Project-based Learning
Prerequisite Skills Basic LabVIEW Familiarity, Basic RIO Familiarity

INCLUDED COURSE LABS

This RT project shows how to make the onboard LED blink and how to create a human interface to control the VI on the RIO target. The project provides step-by-step instructions and serves as an introduction to the different aspects of an RT application. This includes creating a new LabVIEW project, network-published shared variables, an RT VI, PC host VI, and how to set the startup VI for the target. The concepts from this project are utilized through the remaining projects.
This project shows how to build an FPGA VI to blink the LEDs and read the onboard button. You will learn the essential components of a LabVIEW FPGA application, such as creating an FPGA VI, how to test and debug your FPGA VI, and how to create an RT VI to communicate between the FPGA and the HMI running on the host PC. The step-by-step video instructions break the project into nine steps, beginning with how to create a new FPGA project and ending with compiling the FPGA VI to a bitstream file, deploying the network-shared variable, and setting the RT VI to run on the device startup.
In this module, you will learn how to set the administrator password to secure your RIO device, set the time and date, and how to install software add-ons.
The module shows the procedures to create a new project, how to determine the network address of the Academic RIO device, and how to deploy a VI as a start-up application when you power up the RIO device.
This module shows how to access the RT file systems on the device through a web browser. You will learn how to mount the file system as a drive on your Windows, MAC OS, or Linux system and then directly manipulate the files.
This module shows how to interactively monitor signals at the MXP and MSP connectors of the RIO device without creating a VI. This enables you to determine if the digital or analog IOs are working.
This module explains the details of the RIO architecture. You will learn the mechanism by which data from RIO devices communicate with the host PC. There are two sections in this module: PC host, and RT VI. In the PC host section, you will learn how to bind a user interface (UI) indicator with a network-published shared variable. You'll also learn about a common architecture called Event-driven Producer/Consumer State Machine, where a user triggers an event by an action, such as a mouse click. In the RT VI section, you will learn the Queued State Machine architecture to handle the event from the host.
This module introduces you to a Timed Loop, which is a while loop that executes precisely at a user-specified rate. Controlling the timing of your application is one reason to use a high performance real-time operating system (RTO).
Inter-process communication refers to data exchange between two process loops running in parallel. In this module, you will learn different methods to exchange data between a deterministic process loop (predictable timing) and non-deterministic process loop.
In this module, you will learn two methods to exchange data with the FPGA target: front panel communication and direct memory access (DMA). This module will help you determine when it's appropriate to use front panel communication and when it's better to use DMA.
Inter-target communication refers to the exchange of data between a target (FPGA or RT) and the host computer (RT or PC). In this module, you will learn four communication methods for the RT target: front panel communication, network-published shared variables, network streams, and standard communication protocols.
The FPGA bitstream configuration file (“personality”) determines how the RT target interacts with peripheral devices. In this module, you will learn how to access the default personalities and make modifications.
Interrupts suspend the normal code execution to execute a specific task. There are three types of interrupts: digital input transition, analog input threshold, and timer. In this module, you can view video instructions on how to run a callback VI when an interrupt is generated.
Datalogging enables you to write measurement data to a file, timestamp it, and log it. In this module, you will learn how to create a data logging file, update it, and read it. You can save the data file on the RIO device, on your PC, or on a USB drive connected to the RIO device.
Developing your own FPGA-targeted VI provides you with capabilities not available with RT toolkits, such as high-speed I/Os, precision I/O timing, and parallel processing. In this module, you will learn the different methods to program an FPGA, such as creating a LabVIEW VI similar to an RT VI, importing existing VHDL code, or configuring Xilinx IP blocks. You will also learn how to simulate your code before the time-consuming process of compiling, to ensure everything is working. Finally, you will learn how to compile to the FPGA target.
In this module, you will learn how to create a testbench on the PC host to test the sequence of the FPGA VI input. You will learn about the different tools available to help debug your code.
Inter-process communication refers to data exchange between two process loops running in parallel. In this module, you will learn two methods to exchange data in the FPGA using local and global variables.
Inter-target communication refers to the exchange of data between the target (FPGA or RT) and a host computer (RT or desktop PC). In this module, you will learn two methods to exchange data between the FPGA and the host PC or RT target: programmatic front-panel communication and direct memory access.
You can operate a portion of your FPGA code at a rate higher or lower than the 40 MHz onboard system clock by using the derived clock domain. You can control the clock by introducing a delay mechanism to your code or by synchronizing the timing of an external peripheral.
In this module, you will learn how to import or reuse existing VHDL code and Xilinx IP blocks on the LabVIEW block diagram.
In this module, you will download an FPGA personality to the project. You will measure the positive-pulse width waveform at the MSP connector and investigate the jitter from a pulse generated within a conventional while (non-deterministic) loop and a timed (deterministic) loop.
In this module, you will learn how to connect the RIO device to a network. There are three methods: connect to your home wireless network, create an ad-hoc network, or create an Ethernet network with your PC.
In this module, you will learn how to send an email with an attachment to one or more recipients using SMS gateway service.
In this module, you will learn how to exchange information using web services. Your RIO device can call Web Services to retrieve and also to host information for another system to access.
In this module, you will learn about the UDP protocol. It can be used between LabVIEW applications and other IoT devices to send and receive messages.
In this module, you will learn about the TCP protocol. It can be used between LabVIEW applications and other IoT devices to send and receive messages.
In this module, you will learn how to display available IP addresses on the PC host and RT target, and to display your public Internet IP address by calling a Web service.

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Required Software

Learn About Software Licensing
  • NI ELVIS III Software Bundle (2018 or later) - Download Here
    • LabVIEW (Requires license)
    • LabVIEW Real-Time Module (Requires license)
    • LabVIEW NI ELVIS III Toolkit
    • LabVIEW FPGA Module (Requires license)
    • Compilation Tools for Vivado (Requires license)
    • Vision Development Module (Requires license)
    • Vision Acquisition Software (Requires license)

OR

  • myRIO Software Bundle (2013 or later) - Download Here
    • LabVIEW (Requires license)
    • LabVIEW Real-Time Module (Requires license)
    • LabVIEW myRIO Toolkit
    • LabVIEW FPGA Module (Requires license)
    • Compilation Tools for Vivado (Requires license)
    • Vision Development Module (Requires license)
    • Vision Acquisition Software (Requires license)
OR
  • NI ELVIS RIO Control Module Software Bundle (2016 or later) - Download Here
    • LabVIEW (Requires license)
    • LabVIEW Real-Time Module (Requires license)
    • LabVIEW myRIO Toolkit
    • LabVIEW FPGA Module (Requires license)
    • Compilation Tools for Vivado (Requires license)
    • Vision Development Module (Requires license)
    • Vision Acquisition Software (Requires license)
 

Required Hardware

Purchase Engineering Education Products

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Dayna Polstein
06-04-2018 11:04 PM

Hi José. Can you please download again? We made an update that I think will solve the issue. Thanks for commenting.

José Roberto Mateus Fernandes
06-02-2018 10:00 PM

Hi When open the archive in WINRAR this show the message "unexpected end of archive".